1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a system and method for setting threshold voltages using stacked metal gate structures.
2. Description of the Related Art
The threshold voltages (Vth) of the NMOS and PMOS components in a complementary metal oxide semiconductor (CMOS) circuit largely dictate the speed, standby current, and operating current performance characteristics. The Vth must be set to maximize the “on” current, while minimizing the “off” current. Usually this is a trade off that is determined by the circuit design and application. Typically, the Vth is adjusted through the fine-tuning of the doping level in the channel region of the transistors with a Vth adjust implant. As the feature size of transistors continues to scale down, the struggle to minimize short channel effects, and reduce punchthrough and drain-induced barrier lowering with implantations and anneals, ultimately limit the device speed.
As an alternative to adjusting Vth, the work function of the gate can be controlled. This is usually done with implants into the gate polysilicon, where donor type dopant is placed in the gate for NMOS, and acceptor dopants into PMOS gates. The use of doped polysilicon gates presents a different set of problems, however. Dopant diffusion, through the gate dielectric into the channel, affects the Vth and polysilicon depletion near the gate dielectric, and limits the performance of the transistors. This diffusion problem is addressed with the use of metal gate materials.
With metal gate technologies, the choice of an appropriate work function material is necessary for the N and P MOSFETs. Work function is the energy required to remove an electron from the Fermi level to vacuum. The work function of different materials, and even different metals, varies. Since the NMOS and PMOS work function requirements are different, the metal materials are typically different.
Conventional fabrication processes have employed the use of either channel implants combined with the choice of polysilicon or metal gate material. Thus, the work function of the gate has been dictated by the choice of the gate metal material. The fabrication of different gate work functions on the same wafer, such as is required for complementary NMOS and PMOS transistors, has required different gate materials. However, the use of completely different metal materials for use in the NMOS and PMOS gates results in additional fabrication steps and undesired complexity.
Conventionally, the first metal of a gate stack would be isotropically deposited. Then, a photolithographic process would be used to etched away the metal from undesired areas. After that, a second metal can be deposited to complete CMOS gate metal deposition. The underlying gate dielectric potentially faces exposure to an etchant when the undesired first metal areas are removed and is, thus, more susceptible to being thinned, contaminated, and/or damaged.
It would be advantageous if a metal gate stack could be formed without etching the first (bottom) metal in the stack, to minimize damage to the underlying gate dielectric.